ANJU ASOKAN. A Hybrid Test Data Compression Technique for VLSI Circuits. Mathematical Statistician and Engineering Applications, [S. l.], v. 71, n. 4, p. 7255–7266, 2022. DOI: 10.17762/msea.v71i4.1342. Disponível em: https://www.philstat.org/index.php/MSEA/article/view/1342. Acesso em: 2 may. 2024.