SYED NOORULLAH, N VINOD KUMAR, K PRASAD BABU. Implementation of Low Power High Speed CNTFET Adder Subtractor Circuit. Mathematical Statistician and Engineering Applications, [S. l.], v. 71, n. 4, p. 10660–10669, 2022. DOI: 10.17762/msea.v71i4.1959. Disponível em: https://www.philstat.org/index.php/MSEA/article/view/1959. Acesso em: 7 may. 2024.