VIJAY PRAKASH SINGH, LATHA YALLANKI. Study of Performance of Low Power High-Speed Hybrid in 1-Bit Full Adder Circuit. Mathematical Statistician and Engineering Applications, [S. l.], v. 71, n. 2, p. 519–528, 2022. DOI: 10.17762/msea.v71i2.2073. Disponível em: https://www.philstat.org/index.php/MSEA/article/view/2073. Acesso em: 4 may. 2024.