POOJA KRISHNAMURTHY REVANKAR, DR. H. C. HADIMANI, DR. UDARA YEDUKONDALU. Design and Implementation of 64 bit High Speed Floating Point Multiplier for DSP Applications. Mathematical Statistician and Engineering Applications, [S. l.], v. 71, n. 3, p. 767 –, 2022. DOI: 10.17762/msea.v71i3.216. Disponível em: https://www.philstat.org/index.php/MSEA/article/view/216. Acesso em: 28 apr. 2024.