DR. D. R. V. A. SHARATH KUMAR, SUDHIR DAKEY. Increased Clock Gating Efficiency for SRAM and Sequential Circuits. Mathematical Statistician and Engineering Applications, [S. l.], v. 71, n. 3, p. 1029 –, 2022. DOI: 10.17762/msea.v71i3.270. Disponível em: https://www.philstat.org/index.php/MSEA/article/view/270. Acesso em: 29 apr. 2024.