Efficient Puncture and Non Puncture Architecture of Turbo Encoder on FPGA for Advanced Communication System

Abstract

Abstract -This paper concentrates on plan and execution  in-vehicle framework chip with the help of efficient turbo encoder. This module is fostered with the help of FPGA implementation. Both sequential and equal calculations for the encoding strategy are contemplated. Basically two Methodologies were implemented. Fostering the equal calculation technique utilizing convey skip snake, it is shown that both chip size and handling time are gotten to the next level. The rationale usage is improved by diminished region. The Turbo encoder module is planned, recreated, and integrated utilizing Xilinx apparatuses. Xilinx vertex low power is utilized