A Hybrid Test Data Compression Technique for VLSI Circuits

Abstract

VLSI testing ensures that the product designed is defect free and assures the better quality of the products. Testing of a circuit is made possible by the generation of test patterns. The generation of test patterns is necessary for checking the proper functionality of the circuit. As the number of inputs increases, the memory overhead associated with storing the test patterns increases and also the testing time and test cost also increases. To overcome these limitations, test patterns are compressed. In the proposed method, a hybrid test pattern compression scheme is used which uses Burrows Wheeler Transform(BWT), Move To Front Transform and their combination along with several coding schemes on test data sequences. The entire procedure is carried out on ISCAS’ 85 benchmark circuits and the compression ratio for various circuits are computed. The number of transitions between adjacent patterns before and after transform is computed and switching power is also calculated. The area reduced before and after compression is also analyzed.