Design of SRAM Cell with Sense and Precharge Amplifiers

Abstract

In this work the design of SRAM cell using precharge and sense amplifier is proposed. , Embedded SRAM units have become an important block in modern SOC’s. With the rapid growth of transistor count in the SRAM units, the SRAM unit is a power hungry block from both dynamic and static perspectives. One way to design a SRAM cell is to use sense and precharge amplifiers. The sense amplifier is used to read the data stored in the cell, and the precharge amplifier is used to set the initial state of the cell before a read or write operation. The precharge amplifier is activated, which sets the output of the SRAM cell to a known initial state either 0 or 1. The sense amplifier is activated, and it compares the output of the cell with the initial state. If the output has changed, it means that the data stored in the cell has been modified. The sense amplifier amplifies this small change in output, making it easier to detect. Based on the output of the sense amplifier, the data stored in the cell can be determined. If the output of the sense amplifier indicates that the data has not changed, the data stored in the cell is the same as the initial state. If the output of the sense amplifier indicates that the data has changed, the data stored in the cell is the opposite of the initial state. After the read operation is complete, the sense amplifier is deactivated and the precharge amplifier is reactivated, setting the output of the SRAM cell back to the initial state. Overall, the power consumption of a SRAM cell with sense and precharge amplifiers will depend on a variety of factors, including the specific design of the cell and the operating conditions. It is generally considered that SRAM cells are more suitable for applications where low latency and fast access times are more important than power efficiency, whereas DRAM cells are more suitable for applications where power efficiency is a primary concern.