Design of Ultra Low Power DET Flip-Flop with Power Gating Technique

Abstract

The advancement of battery operated designs have abundantly increases the memory elements and registers to be operated in ultra low power. That is the this paper we have proposed a design of CT_C DET flip-flop with power gating technique which is the most efficient power consuming reduction technique.  The design of the power gating technique involves the pull-up transistor in the Vdd of the circuit and pull-down transistor in the Gnd terminal. This power gating technique reduces the power consumption by more than 40% than that of the existing design.