Dynamic Power Reduction Using Switching Activity based Multibit Re-Ordering

Abstract

In today’s application world there is demand of devices which operate on low power, so power is an important sign-off metric. There are many low power techniques like clock-gating, power gating, Dynamic voltage and frequency scaling which are adopted in design flow to help reduce consumption of power by integrated circuits. Multibit banking is a technique where more than one registers having common clock and asynchronous input lines are mapped to one library cell having multiple bits which avoids separate clock and other asynchronous lines. This reduces switching activity and helps reduce dynamic power and area.  Use of multibit cells has become part of design flow. This work aims at using multibit in design flow and re-ordering of the bits based on scan switching activity so that bits with low switching activity is used as scan-out of the multibit cell during scan shifting.