A New Method for Reducing Voltage Sag Using Interline Dynamic Voltage Restorer

Abstract

Power quality is of immense importance in all modern environments where electricity is involved. Power quality can be essentially influenced by important factor like quality service. Power quality problems were categorized by five major events; sags, swells, transients, interruptions and harmonics. These problems may cause degradation in services which can cost economic losses to both utility and consumers. The power quality problems originate from various events ranging from switching events at the end user facility or faults on transmission lines. The extensive use of equipment sensitive to voltage deviation has made industrial applications more susceptible to voltage sags and swells. Among these the sags appeared as a top concern. Voltage sags can cause improper functioning and eventual tripping of industrial equipment, resulting in loss of production and hence profit. Voltage sag mitigation can be done using dynamic voltage restorer (DVR) and inter-line dynamic voltage restorer (IDVR). One of the main factors which limit capabilities of DVR in compensating long-duration voltage sags is the amount of stored energy within the restorer. In order to overcome this limitation, IDVR has been proposed where two DVR’s each compensating a transmission line by series voltage injection, connected with common dc-link. In this work, I am concentrating on modelling and simulation of IDVR using SVPWM technique to mitigate voltage in the power line by MATLAB/SIMULINK software.