A Performance Analysis of Cmos-Based Design for A Finfet Sram Cell

Abstract

SRAM cells based on long channel devices are somewhat more resilient than optimised SRAM, but the higher gate-edge direct tunnelling leakage and parasitic capacitances decrease the power usage. SRAM cell leakage has to be minimised if the cell is to be made more stable. As a result, a variety of low-power approaches are employed to minimise power dissipation and leakage currents. The static noise margin of FinFET-based SRAM cells with built-in feedback is shown to be significantly improved without read/write in time analysis when designed with built-in feedback. SRAM cells based on FINFET technology are preferred over CMOS-based SRAM cells because they offer a shorter access time, lower power consumption, and lower leakage current. In this aspect, FinFET is a promising technology that is advancing. The SRAM cell device is designed, modelled, and optimised in this paper.