A Novel Design of High Speed Memory-Based FFT Processor Using Adaptive Technique

Abstract

In this paper a novel design of high speed memory based FFT processor using adaptive technique is implemented. FFT is mainly used in the applications of high speed. Initially, input index vector generator will take inputs and transfer the inputs to scaling unit controls the scaling operations and transfer those bits to the BAGU unit. Memory bank address and address generation unit will generate the address to obtain data and saved in the memory-1 block. Similarly same operation is performed and saved that data in memory-2 block. All these data will be computed using p×p compotator. The computed data is multiplied using modular multiplication unit. The obtained multiplied data is transferred to the BFP unit which is nothing but block floating point. From results it can observe that proposed system gives effective results in terms of delay and area.