FPGA Implementation of UaL Decomposition, an alternative to the LU factorization

Abstract

Matrix decomposition is an important method used in many applications such as circuit simulations, for example Modified Nodal Analysis (MNA matrices), and in communication systems, for example to find minimum mean square error (MMSE) in MIMO systems for detecting the transmitted symbol vector from the received symbol vector. In this paper, an FPGA based hardware implementation of an alternative solution to LU factorization technique called UaL decomposition method is proposed. The RTL code of the UaL algorithm is developed and simulated using Xilinx Vivado software. The RTL code of the proposed FPGA based UaL decomposition hardware architecture is synthesized by targeting Virtex-5 FPGA which supports the data input in single-precision Floating-point representation format. The FPGA implementation of the UaL decomposition method is compared with the existing FPGA implementations of LU, LDL, Cholesky and QR decomposition methods in terms of area, frequency and computational time. The proposed sequential FPGA implementation of UaL decomposition utilizes 47% less resources than the existing best parallel LU factorization FPGA implementation but requires 50% more computational time, and operates at 210 MHz which is approximately three times than the operating frequency of best existing decomposition implementation (LU decomposition). The parallel implementation of UaL decomposition is expected to reduce the computational time by 32% compared to sequential UaL and 68.9% compared to LU decomposition.